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Top FPGA

Description

Top-Level of the FPGA.

Overview

The following figure depicts the Top-Level:

Generics

Generic Name Type Default Value Description
G_GIT_ID vector[31:0] 0x0000 Git ID containing the sources for the bitstream generation. Automatically set by the run_synthesis. tcl script.

Inputs and Outputs

Port Name Type Direction Default Value Description
PAD_I_CLK std_logic in - Input clock
PAD_I_RST_H std_logic in - Input asynchronous reset, active high
PAD_I_UART_RX std_logic in - Input UART RX line
PAD_O_UART_TX std_logic out 0b1 Output UART TX line
PAD_O_SCLK std_logic out 0b0 Output SPI serial clock
PAD_O_MOSI std_logic out 0b0 Output SPI Master Output Slave Input
PAD_I_MISO std_logic in - Output SPI Master Input Slave Input
PAD_O_CS_N std_logic out 0b1 Output SPI Chip Select
O_HSYNC std_logic out 0b0 Horizontal sync signal output
O_VSYNC std_logic out 0b0 Vertical sync signal output
O_RED vector[3:0] out 0x00 Red color channel output (blanked during inactive regions)
O_GREEN vector[3:0] out 0x00 Green color channel output (blanked during inactive regions)
O_BLUE vector[3:0] out 0x00 Blue color channel output (blanked during inactive regions)
PAD_I_SWITCH_0 std_logic in - Input switch 0
PAD_I_SWITCH_1 std_logic in - Input switch 1
PAD_I_SWITCH_2 std_logic in - Input switch 2
PAD_O_LED_0 std_logic out 0b1 Output LED 0

Architecture

Internal Reset

The FPGA internal reset internal_rst_n signal is generated by combining two conditions:

  1. The external reset button PAD_I_RST_H (active-high)
  2. The PLL lock status pll_locked

This ensures that the internal logic remains in reset until both the reset button is released or the PLL is unlocked.

Then, the FPGA resynchronize the asynchronous reset signal to both clock domain to ensure synchronous de-assertion of the reset.

The FPGA instantiates the olo_base_reset_gen module with the following generics for the system clock domain reset:

Generic Name Type Default Value Description
RstPulseCycles_g positive 0d3 Minimum duration of the reset pulse in clock cycles
RstInPolarity_g std_logic 0b1 Polarity of 'RstIn'.
AsyncResetOutput_g boolean false False -> Reset signal is asserted synchronously.
SyncStages_g positive 0d3 Number of synchronization stages for the multi-stage synchronizer.

The FPGA instantiates the olo_base_reset_gen module with the following generics for the VGA clock domain reset:

Generic Name Type Default Value Description
RstPulseCycles_g positive 0d3 Minimum duration of the reset pulse in clock cycles
RstInPolarity_g std_logic 0b1 Polarity of 'RstIn'.
AsyncResetOutput_g boolean false False -> Reset signal is asserted synchronously.
SyncStages_g positive 0d3 Number of synchronization stages for the multi-stage synchronizer.

olo_intf_sync

The FPGA instantiates the olo_intf_sync module with the following generics:

Generic Name Type Default Value Description
Width_g positive 0d3 Number of data bits
RstLevel_g std_logic 0b000 Value to set the synchronizer registers to upon reset.
SyncStages_g positive 0b000 Number of synchronization stages.

UART

The FPGA instantiates the uart module with the following generics:

Generic Name Type Default Value Description
G_CLK_FREQ_HZ positive 0d50_000_000 Clock frequency in Hz of internal_clk
G_BAUD_RATE_BPS positive 0d115_200 Baud rate in bps
G_SAMPLING_RATE positive 0d16 Sampling rate (number of clock cycles per bit)

Regfile

The FPGA instantiates the regfile module with the following generics:

Generic Name Type Default Value Description
G_GIT_ID_MSB vector[15:0] G_GIT_ID[31:16] 16 MSB of the git ID containing the sources for the bitstream generation
G_GIT_ID_LSB vector[15:0] G_GIT_ID[15:0] 16 LSB of the git ID containing the sources for the bitstream generation

SPI Master

The FPGA instantiates the spi_master module with the following generics:

Generic Name Type Default Value Description
G_CLK_FREQ_HZ positive 0d50_000_000 Clock frequency in Hz of internal_clk
G_SPI_FREQ_HZ positive 0d1_000_000 SPI clock frequency in Hz
G_NB_DATA_BITS positive 0d8 Number of data bits within the SPI transaction
G_CLK_POLARITY std_logic 0b0 Generated SPI clock polarity
G_CLK_PHASE std_logic 0b0 Generated SPI clock phase

VGA

The FPGA instantiates the vga_controller module with the following generics:

Generic Name Type Default Value Description
G_H_PIXELS integer 0d1024 Horizontal resolution in pixels
G_H_FRONT_PORCH integer 0d24 Horizontal front porch in pixels
G_H_SYNC_PULSE integer 0d136 Horizontal synchronization pulse in pixels
G_H_BACK_PORCH integer 0d160 Horizontal back porch in pixels
G_V_PIXELS integer 0d768 Vertical resolution in pixels
G_V_FRONT_PORCH integer 0d3 Vertical front porch in pixels
G_V_SYNC_PULSE integer 0d6 Vertical synchronization pulse in pixels
G_V_BACK_PORCH integer 0d29 Vertical back porch in pixels