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Testcase Descriptions


Testcase 01: test_top_fpga_registers

Description

Checks default values and access rights (RO/RW) for the test registers of the FPGA.

Steps

  1. Reset the DUT

  2. Check Default Register Values

    Call proc_uart_check_default_value and verify value after reset.

  3. Verify Read-Only Registers

  4. Verify Read-Write Registers

  5. Write and Verify Custom Value

    • Write 0xABCD to C_REG_16_BITS.
    • Read back and check value is 0xABCD.

Testcase 02: test_uart_robustness

Description

Tests robustness of UART implementation including invalid start/stop bits and command framing.

Steps

  1. Reset the DUT

  2. Send Read Command With Invalid Start Bit in 'R'

    • Set manual UART: tb_i_uart_select to 1
    • Manipulate tb_i_uart_rx_manual as follows:
      1. Set to 0, wait 0.25 × C_UART_BIT_TIME (invalid start bit)
      2. Set to 1, wait 0.75 × C_UART_BIT_TIME
      3. Set to 0, wait C_UART_BIT_TIME (bit 0)
      4. Set to 1, wait C_UART_BIT_TIME (bit 1)
      5. Set to 0, wait C_UART_BIT_TIME (bit 2)
      6. Set to 0, wait C_UART_BIT_TIME (bit 3)
      7. Set to 1, wait C_UART_BIT_TIME (bit 4)
      8. Set to 0, wait C_UART_BIT_TIME (bit 5)
      9. Set to 1, wait C_UART_BIT_TIME (bit 6)
      10. Set to 0, wait C_UART_BIT_TIME (bit 7)
      11. Send stop bit (1), 1.1 × wait C_UART_BIT_TIME
    • Send bytes 0x30, 0x30, 0x0D using proc_uart_send_byte
    • Wait 1.1 × C_UART_READ_CMD_TIME
    • Check UART TX is stable high: tb_pad_o_uart_tx remains 1 for C_UART_READ_CMD_TIME with check_equal
  3. Send Read Command With Invalid Stop Bit in 'R'

    • Call proc_reset_dut
    • Wait for 100 µs
    • Set tb_i_uart_select to 1
    • Manipulate tb_i_uart_rx_manual as follows:
      1. Send start bit (0), wait C_UART_BIT_TIME
      2. Set to 0, wait C_UART_BIT_TIME (bit 0)
      3. Set to 1, wait C_UART_BIT_TIME (bit 1)
      4. Set to 0, wait C_UART_BIT_TIME (bit 2)
      5. Set to 0, wait C_UART_BIT_TIME (bit 3)
      6. Set to 1, wait C_UART_BIT_TIME (bit 4)
      7. Set to 0, wait C_UART_BIT_TIME (bit 5)
      8. Set to 1, wait C_UART_BIT_TIME (bit 6)
      9. Set to 0, wait C_UART_BIT_TIME (bit 7)
      10. Send invalid stop bit (0), 1.1 × wait C_UART_BIT_TIME
    • Send bytes 0x30, 0x30, 0x0D using proc_uart_send_byte
    • Wait 1.1 × C_UART_READ_CMD_TIME
    • Check UART TX is stable high: tb_pad_o_uart_tx remains 1 for C_UART_READ_CMD_TIME with check_equal
  4. Check UART Timings With Value 0x5555

  5. Send Read Commands With Invalid CR

    • Call proc_reset_dut
    • Wait for 100 µs
    • Send bytes: 0x52, 0x30, 0x31, 0x0A (missing CR)
    • Wait C_UART_READ_CMD_TIME
    • Check TX remains 1 for duration
  6. Send Write Command With Invalid CR


Testcase 03: test_led_and_switches_toggling

Description

Validates REG_LED (read-write) and REG_SWITCHES (read-only). Checks toggling the LED output and reading all switch combinations.

Steps

  1. Check Register REG_LED Characteristics

  2. Toggle led_0 Register and Verify Output

    • Write 0x0001 to C_REG_LED Wait for 1 ms Check tb_pad_o_led_0 is stable at '1' for 0.7 ms using check_equal
    • Write 0x0000 to C_REG_LED Wait for 2.5 ms Check tb_pad_o_led_0 is stable at '0' for 2.3 ms
    • Write 0x0001 to C_REG_LED Wait for 2 ms Check tb_pad_o_led_0 is stable at '1' for 1.8 ms
  3. Check Register REG_SWITCHES Characteristics

  4. Toggle Input Switches and Verify Combinations

    • For all combinations of tb_pad_i_switch_0, tb_pad_i_switch_1, tb_pad_i_switch_2 (from 0 to 7):
      • Set switches with binary pattern from i
      • Wait for 1 ns (signal propagation)
      • Check register C_REG_SWITCHES value matches the bit pattern using proc_uart_check

Testcase 04: test_spi

Description

Tests SPI master TX and RX registers, including SPI transfer correctness and MOSI/MISO data verification.

Steps

  1. Reset DUT and Check Register Default Values

  2. Testing SPI output

  3. Testing SPI timings

    • Call proc_reset_dut
    • Wait for 100 µs
    • Set tb_check_spi_timings to 1
    • Wait for 2 × C_CLK_PERIOD
    • Set tb_check_spi_timings to 0
    • Send an SPI transaction with data set to 0x55 using proc_spi_write
    • Wait for 2 × C_SPI_TRANSACTION_TIME (time longer than the response)
    • Set tb_check_spi_timings to 1
    • Wait for 2 × C_CLK_PERIOD
    • Set tb_check_spi_timings to 0
    • Send an SPI transaction with data set to 0xAB using proc_spi_write
    • Wait for 2 × C_SPI_TRANSACTION_TIME (time longer than the response)