Entity: permutation

Diagram

clock reset_n i_sys_enable i_mux_select i_enable_xor_key_begin i_enable_xor_data_begin i_enable_xor_key_end i_enable_xor_lsb_end i_enable_cipher_reg i_enable_tag_reg i_enable_state_reg t_state_array i_state [ 3:0] i_round [ 63:0] i_data [127:0] i_key t_state_array o_state [ 63:0] o_cipher [127:0] o_tag

Ports

Port name Direction Type Description
clock input Clock signal
reset_n input Reset signal, active low
i_sys_enable input System enable signal, active high
i_mux_select input Mux select signal, active high
i_enable_xor_key_begin input Enable XOR with Key, active high
i_enable_xor_data_begin input Enable XOR with Data, active high
i_enable_xor_key_end input Enable XOR with Key, active high
i_enable_xor_lsb_end input Enable XOR with LSB, active high
i_enable_cipher_reg input Enable cipher register, active high
i_enable_tag_reg input Enable tag register, active high
i_enable_state_reg input Enable state register, active high
i_state input t_state_array Input state array
i_round input [ 3:0] Input round number
i_data input [ 63:0] Input data
i_key input [127:0] Input key
o_state output t_state_array Output state array
o_cipher output [ 63:0] Output cipher
o_tag output [127:0] Output tag

Signals

Name Type Description
o_cipher_reg logic [ 63:0] Output of the cipher register
o_tag_reg logic [127:0] Output of the tag register

Processes

Type: always_ff

Instantiations