Entity: ascon_fsm

• File: ascon_fsm.sv

Diagram

Ports

Port name	Direction	Type	Description
clock	input		Clock signal
reset_n	input		Reset signal, active low
i_sys_enable	input		System enable signal, active high
i_start	input		Start signal, active high
i_data_valid	input		Data valid signal, active high
i_round_count	input	[3:0]	Round Counter value
i_block_count	input	[1:0]	Block Counter value
o_valid_cipher	output		Cipher valid signal
o_done	output		End of Ascon signal
o_mux_select	output		Mux select signal (low=input, high=outputreg)
o_enable_xor_data_begin	output		Enable XOR with Data, active high
o_enable_xor_key_begin	output		Enable XOR with Key, active high
o_enable_xor_key_end	output		Enable XOR with Key, active high
o_enable_xor_lsb_end	output		Enable XOR with LSB, active high
o_enable_state_reg	output		Enable state register, active high
o_enable_cipher_reg	output		Enable cipher register, active high
o_enable_tag_reg	output		Enable tag register, active high
o_enable_round_counter	output		Enable round counter, active high
o_reset_round_counter_to_6	output		Reset round counter, active high
o_reset_round_counter_to_0	output		Reset round counter, active high
o_enable_block_counter	output		Enable block counter, active high
o_reset_block_counter	output		Count block start signal, active high

Types

Name	Type	Description
type_state_e	enum logic unsigned [4:0] { STATE_IDLE, STATE_CONFIGURATION, STATE_START_INITIALIZATION, STATE_PROCESS_INITIALIZATION, STATE_END_INITIALIZATION, STATE_IDLE_ASSOCIATED_DATA, STATE_START_ASSOCIATED_DATA, STATE_PROCESS_ASSOCIATED_DATA, STATE_END_ASSOCIATED_DATA, STATE_IDLE_PLAIN_TEXT, STATE_START_PLAIN_TEXT, STATE_PROCESS_PLAIN_TEXT, STATE_END_PLAIN_TEXT, STATE_IDLE_FINALIZATION, STATE_START_FINALIZATION, STATE_PROCESS_FINALIZATION, STATE_END_FINALIZATION }

Processes

• unnamed: ( @(posedge clock or negedge reset_n) )

• unnamed: ( )

• unnamed: ( )

State machines