Entity: ascon

Diagram

clock reset_n i_sys_enable i_start i_data_valid [ 63:0] i_data [127:0] i_key [127:0] i_nonce [ 63:0] o_cipher [127:0] o_tag o_valid_cipher o_done

Description

Timing diagram for the ASCON-128 encryption with this implementation. One Permutation per clock cycle.


ASCON-128 Encryption Timing Diagram0123456789101112131415161718192021222324252627282930313233Clock & Controlclockreset_ni_sys_enablei_startInput Signalsi_data_validi_data0x0000...0000Block1Block2 Block5i_key Key i_nonce NonceOutput Signalso_cipher0x0000...0000Cipher1Cipher4o_valid_ciphero_tag0x0000...0000Tago_done

Ports

Port name Direction Type Description
clock input Clock signal
reset_n input Reset signal, active low
i_sys_enable input System enable signal, active high
i_start input Start signal, active high
i_data_valid input Data valid signal, active high
i_data input [ 63:0] Data input
i_key input [127:0] Key input
i_nonce input [127:0] Nonce input
o_cipher output [ 63:0] Cipher output
o_tag output [127:0] Tag output
o_valid_cipher output Valid cipher output
o_done output Done signal

Signals

Name Type Description
s_mux_select logic
s_enable_xor_data_begin logic
s_enable_xor_key_begin logic
s_enable_xor_key_end logic
s_enable_xor_lsb_end logic
s_enable_state_reg logic
s_enable_cipher_reg logic
s_enable_tag_reg logic
s_enable_round_counter logic
s_reset_round_counter_to_6 logic
s_reset_round_counter_to_0 logic
s_enable_block_counter logic
s_reset_block_counter logic
s_valid_cipher logic
reg_valid_cipher logic
s_done logic
reg_done logic
reg_round_counter logic [3:0] Round counter Signal
reg_block_counter logic [1:0] Block counter Signal

Processes

Type: always_ff

Instantiations