ascon-verilog Documentation

Introduction

This project provides synthesizable implementations of the Ascon 128 algorithm in both SystemVerilog and VHDL, using open-source tools. You can choose between two equivalent implementations:

• SystemVerilog implementation: Complete RTL design tested using Cocotb-based testbenches

• VHDL implementation: Functionally equivalent RTL design tested using VUnit-based testbenches

The project is organized as follows:

1. The src/rtl directory contains both SystemVerilog and VHDL modules for the Ascon 128 algorithm.

2. The src/bench directory contains the verification environments: Cocotb testbenches for SystemVerilog modules and VUnit testbenches for VHDL modules.

This project is an improvement of a project I did during my studies at the École des Mines de Saint-Étienne.

You can find a Cocotb Presentation at the root of the repository.

Table of Contents

• Getting Started
• Ascon Implementation
• HDL Modules
• Python Modules
• References

Installation

To get started with the project, follow the installation instructions provided in the Getting Started guide.