ascon-verilog Documentation

Introduction

This project provides a synthesizable implementation of the Ascon 128 algorithm in Verilog, using open-source tools. The project is divided into two main parts:

1. The src/rtl directory contains the Verilog modules for the Ascon 128 algorithm.

2. The src/bench directory contains the python testbenches for the Ascon 128 algorithm.

This project is an improvement of a project I did during my studies at the École des Mines de Saint-Étienne.

You can find a Cocotb Presentation at the root of the repository.

Table of Contents

• Getting Started
• Ascon Implementation
• HDL Modules
• Python Modules
• References

Installation

To get started with the project, follow the installation instructions provided in the Getting Started guide.